137 lines
1.8 KiB
Text
137 lines
1.8 KiB
Text
#
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## Libraries
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snippet lib
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library ${1}
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use $1.${2}
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# Standard Libraries
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snippet libs
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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# Xilinx Library
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snippet libx
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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## Entity Declaration
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snippet ent
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entity ${1:`vim_snippets#Filename()`} is
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generic (
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${2}
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);
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port (
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${3}
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);
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end entity $1;
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## Architecture
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snippet arc
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architecture ${1:behav} of ${2:`vim_snippets#Filename()`} is
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${3}
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begin
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end $1;
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## Declarations
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# std_logic
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snippet st
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signal ${1} : std_logic;
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# std_logic_vector
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snippet sv
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signal ${1} : std_logic_vector (${2} downto 0);
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# std_logic in
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snippet ist
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${1} : in std_logic;
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# std_logic_vector in
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snippet isv
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${1} : in std_logic_vector (${2} downto 0);
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# std_logic out
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snippet ost
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${1} : out std_logic;
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# std_logic_vector out
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snippet osv
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${1} : out std_logic_vector (${2} downto 0);
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# unsigned
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snippet un
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signal ${1} : unsigned (${2} downto 0);
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## Process Statements
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# process
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snippet pr
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process (${1})
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begin
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${2}
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end process;
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# process with clock
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snippet prc
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process (${1:clk})
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begin
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if rising_edge ($1) then
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${2}
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end if;
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end process;
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# process with clock and reset
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snippet prcr
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process (${1:clk}, ${2:nrst})
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begin
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if ($2 = '${3:0}') then
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${4}
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elsif rising_edge($1) then
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${5}
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end if;
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end process;
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# process all
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snippet pra
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process (${1:all})
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begin
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${2}
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end process;
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## Control Statements
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# if
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snippet if
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if ${1} then
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${2}
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end if;
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# if
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snippet ife
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if ${1} then
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${2}
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else
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${3}
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end if;
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# else
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snippet el
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else
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${1}
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# if
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snippet eif
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elsif ${1} then
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${2}
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# case
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snippet ca
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case ${1} is
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${2}
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end case;
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# when
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snippet wh
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when ${1} =>
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${2}
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# for
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snippet for
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for ${1:i} in ${2} ${3:to} ${4} loop
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${5}
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end loop;
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# while
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snippet wh
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while ${1} loop
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${2}
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end loop;
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## Misc
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# others
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snippet oth
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(others => '${1:0}');
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