73 lines
1.2 KiB
Text
73 lines
1.2 KiB
Text
extends verilog
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# Foreach Loop
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snippet forea
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foreach (${1}) begin
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${0}
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end
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# Do-while statement
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snippet dowh
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do begin
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${0}
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end while (${1});
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# Combinational always block
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snippet alc
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always_comb begin ${1:: statement_label}
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${0}
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end $1
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# Sequential logic
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snippet alff
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always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
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${0}
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end $2
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# Latched logic
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snippet all
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always_latch begin ${1:: statement_label}
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${0}
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end $1
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# Class
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snippet cl
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class ${1:class_name};
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// data or class properties
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${0}
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// initialization
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function new();
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endfunction : new
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endclass : $1
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# Typedef structure
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snippet types
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typedef struct {
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${0}
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} ${1:name_t};
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# Program block
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snippet prog
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program ${1:program_name} ();
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${0}
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endprogram : $1
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# Interface block
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snippet intf
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interface ${1:program_name} ();
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// nets
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${0}
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// clocking
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// modports
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endinterface : $1
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# Clocking Block
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snippet clock
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clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
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${0}
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endclocking : $1
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# Covergroup construct
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snippet cg
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covergroup ${1:group_name} @(${2:posedge} ${3:clk});
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${0}
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endgroup : $1
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# Package declaration
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snippet pkg
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package ${1:package_name};
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${0}
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endpackage : $1
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